module SingleCycleProcessor(Clk, RESET        , M0, M1, M5, M16, M17); //Ms for test;
input Clk, RESET;

	output [7:0] M0, M1, M5, M16, M17; //for test

wire [5:0] Opcode, Function;
wire [2:0] ALUOp;
wire RegDst, Jump, Branch, MemtoReg, MemWrite, ALUSrc, RegWrite;

SingleCycleDatapath Datapath(
.Clk(Clk),
.RegDst(RegDst), 
.Jump(Jump), 
.Branch(Branch), 
.MemtoReg(MemtoReg), 
.MemWrite(MemWrite), 
.ALUSrc(ALUSrc), 
.RegWrite(RegWrite), 
.Instruction31_26(Opcode), 
.Instruction5_0(Function), 
.RESET(RESET), 
.ALUOperation(ALUOp)
, .M0(M0), .M1(M1), .M5(M5), .M16(M16), .M17(M17)//for test
);

Control ControlUnit(
.iOpcode(Opcode),
.iFunction(Function),
.oRegWrite(RegWrite),
.oRegDst(RegDst),
.oALUSrc(ALUSrc),
.oALUOp(ALUOp),
.oMemWrite(MemWrite),
.oMemtoReg(MemtoReg),
.oPCSrc(Branch),
.oJump(Jump)
);

endmodule